1 : /*
2 : * Copyright (c) 2012 The Native Client Authors. All rights reserved.
3 : * Use of this source code is governed by a BSD-style license that can be
4 : * found in the LICENSE file.
5 : */
6 :
7 : /*
8 : * This file contains common parts of ia32 and x86-64 decoder and validator
9 : * internals (inline functions which are used to pull useful information from
10 : * "well-known" bytes of the instruction: REX and VEX prefixes, ModR/M byte and
11 : * so on).
12 : *
13 : * See full description in AMD/Intel manuals.
14 : */
15 :
16 : #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_RAGEL_DECODING_H_
17 : #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_RAGEL_DECODING_H_
18 :
19 : #include "native_client/src/trusted/validator_ragel/decoder.h"
20 :
21 : #if NACL_WINDOWS
22 : # define FORCEINLINE __forceinline
23 : #else
24 : # define FORCEINLINE __inline __attribute__ ((always_inline))
25 : #endif
26 :
27 :
28 : /*
29 : * Opcode-with-register byte format:
30 : *
31 : * bits 0-2: register number
32 : * bits 3-7: actual opcode
33 : */
34 1 : static FORCEINLINE uint8_t RegFromOpcode(uint8_t modrm) {
35 1 : return modrm & 0x07;
36 1 : }
37 :
38 : /*
39 : * ModRM byte format:
40 : *
41 : * bits 0-2: r/m
42 : * bits 3-5: reg
43 : * bits 6-7: mod
44 : */
45 : static FORCEINLINE uint8_t ModFromModRM(uint8_t modrm) {
46 : return modrm >> 6;
47 : }
48 :
49 1 : static FORCEINLINE uint8_t RegFromModRM(uint8_t modrm) {
50 1 : return (modrm >> 3) & 0x07;
51 1 : }
52 :
53 1 : static FORCEINLINE uint8_t RMFromModRM(uint8_t modrm) {
54 1 : return modrm & 0x07;
55 1 : }
56 :
57 : /*
58 : * SIB byte format:
59 : *
60 : * bits 0-2: base
61 : * bits 3-5: index
62 : * bits 6-7: scale
63 : */
64 : static FORCEINLINE uint8_t ScaleFromSIB(uint8_t sib) {
65 : return sib >> 6;
66 : }
67 :
68 1 : static FORCEINLINE uint8_t IndexFromSIB(uint8_t sib) {
69 1 : return (sib >> 3) & 0x07;
70 1 : }
71 :
72 1 : static FORCEINLINE uint8_t BaseFromSIB(uint8_t sib) {
73 1 : return sib & 0x07;
74 1 : }
75 :
76 : /*
77 : * REX byte format:
78 : *
79 : * bit 0: B (Base)
80 : * bit 1: X (indeX)
81 : * bit 2: R (Register)
82 : * bit 3: W (Wide)
83 : * 4-7 bits: 0x4 (REX signature)
84 : */
85 :
86 : enum {
87 : REX_B = 1,
88 : REX_X = 2,
89 : REX_R = 4,
90 : REX_W = 8
91 : };
92 :
93 : /* How much to add to "base register" number: 0 or 8 */
94 1 : static FORCEINLINE uint8_t BaseExtentionFromREX(uint8_t rex) {
95 1 : return (rex & REX_B) << 3;
96 1 : }
97 :
98 : /* How much to add to "index register" number: 0 or 8 */
99 1 : static FORCEINLINE uint8_t IndexExtentionFromREX(uint8_t rex) {
100 1 : return (rex & REX_X) << 2;
101 1 : }
102 :
103 : /* How much to add to "register operand" number: 0 or 8 */
104 1 : static FORCEINLINE uint8_t RegisterExtentionFromREX(uint8_t rex) {
105 1 : return (rex & REX_R) << 1;
106 1 : }
107 :
108 : /*
109 : * VEX 2nd byte format:
110 : *
111 : * bits 0-4: opcode selector
112 : * bit 5: inverted B (Base)
113 : * bit 6: inverted X (indeX)
114 : * bit 7: inverted R (Register)
115 : *
116 : */
117 :
118 : enum {
119 : VEX_MAP1 = 0x01,
120 : VEX_MAP2 = 0x02,
121 : VEX_MAP3 = 0x03,
122 : VEX_MAP8 = 0x08,
123 : VEX_MAP9 = 0x09,
124 : VEX_MAPA = 0x0a,
125 : VEX_B = 0x20,
126 : VEX_X = 0x40,
127 : VEX_R = 0x80
128 : };
129 :
130 : /* How much to add to "base register" number: 0 or 8 */
131 1 : static FORCEINLINE uint8_t BaseExtentionFromVEX(uint8_t vex2) {
132 1 : return ((~vex2) & VEX_B) >> 2;
133 1 : }
134 :
135 : /* How much to add to "index register" number: 0 or 8 */
136 1 : static FORCEINLINE uint8_t IndexExtentionFromVEX(uint8_t vex2) {
137 1 : return ((~vex2) & VEX_X) >> 3;
138 1 : }
139 :
140 : /* How much to add to "register operand" number: 0 or 8 */
141 1 : static FORCEINLINE uint8_t RegisterExtentionFromVEX(uint8_t vex2) {
142 1 : return ((~vex2) & VEX_R) >> 4;
143 1 : }
144 :
145 : /*
146 : * VEX 3rd byte format:
147 : *
148 : * bits 0-1: pp (Packed Prefix)
149 : * bit 2: L (Long)
150 : * bits 3-6: negated vvvv (register number)
151 : * bit 7: W (Wide)
152 : */
153 :
154 : enum {
155 : VEX_PP_NONE = 0x00,
156 : VEX_PP_0X66 = 0x01,
157 : VEX_PP_0XF3 = 0x02,
158 : VEX_PP_0XF2 = 0x03,
159 : VEX_L = 0x04,
160 : VEX_VVVV = 0x78,
161 : VEX_W = 0x80
162 : };
163 :
164 :
165 : static FORCEINLINE uint8_t GetOperandFromVexIA32(uint8_t vex3) {
166 : return ((~vex3) & VEX_VVVV) >> 3;
167 : }
168 :
169 0 : static FORCEINLINE uint8_t GetOperandFromVexAMD64(uint8_t vex3) {
170 0 : return ((~vex3) & VEX_VVVV) >> 3;
171 0 : }
172 :
173 : /*
174 : * is4/is5 byte format:
175 : *
176 : * bits 0-1: imm2 or zero
177 : * bits 2-3: 0
178 : * bits 4-7: register number
179 : */
180 : static FORCEINLINE uint8_t RegisterFromIS4(uint8_t is4) {
181 : return is4 >> 4;
182 : }
183 :
184 : /*
185 : * SignExtendXXBit is used to sign-extend XX-bit value to unsigned 64-bit value.
186 : *
187 : * To do that you need to pass unsigned value of smaller then 64-bit size
188 : * to this function: it will be converted to signed value and then
189 : * sign-extended to become 64-bit value.
190 : *
191 : * Return values can be restricted to smaller unsigned type when needed (which
192 : * is safe according to the C language specification: see 6.2.1.2 in C90 and
193 : * 6.3.1.3.2 in C99 specification).
194 : *
195 : * Note that these operations are safe but slightly unusual: they come very
196 : * close to the edge of what "well-behaved C program is not supposed to do",
197 : * but they stay on the "safe" side of this boundary. Specifically: this
198 : * (conversion to intXX_t) behavior triggers "implementation-defined behavior"
199 : * (see 6.2.1.2 in C90 specification and 6.3.1.3.3 in C99 specification) which
200 : * sounds suspiciously similar to the dreaded "undefined behavior", but in
201 : * reality these two are quite different: any program which triggers "undefined
202 : * behavior" is not a valid C program at all, but program which triggers
203 : * "implementation-defined behavior" is quite valid C program. What this
204 : * program actually *does* depends on the specification of a given C compiler:
205 : * each particular implementation must decide for itself what it'll do in this
206 : * particular case and *stick* *to* *it*. If the implementation actually uses
207 : * two's-complement negative numbers (and all the implementation which can
208 : * compile this code *must* support two's-complement arythmetic - see 7.18.1.1
209 : * in C99 specification) then the easiest thing to do is to do what we need
210 : * here - this is what all known compilers for all known platforms are actually
211 : * doing.
212 : *
213 : * Conversion from intXX_t to uint64_t is always safe (same as before: see
214 : * see 6.2.1.2 in C90 specification and 6.3.1.3.2 in C99 specification).
215 : */
216 : static FORCEINLINE uint64_t SignExtend8Bit(uint64_t value) {
217 : return (int8_t)value;
218 : }
219 :
220 : static FORCEINLINE uint64_t SignExtend16Bit(uint64_t value) {
221 : return (int16_t)value;
222 : }
223 :
224 : static FORCEINLINE uint64_t SignExtend32Bit(uint64_t value) {
225 : return (int32_t)value;
226 : }
227 :
228 : static FORCEINLINE uint64_t AnyFieldValue8bit(const uint8_t *start) {
229 : return *start;
230 : }
231 :
232 : static FORCEINLINE uint64_t AnyFieldValue16bit(const uint8_t *start) {
233 : return (start[0] + 256U * start[1]);
234 : }
235 :
236 : static FORCEINLINE uint64_t AnyFieldValue32bit(const uint8_t *start) {
237 : return (start[0] + 256U * (start[1] + 256U * (start[2] + 256U * (start[3]))));
238 : }
239 : static FORCEINLINE uint64_t AnyFieldValue64bit(const uint8_t *start) {
240 : return (*start + 256ULL * (start[1] + 256ULL * (start[2] + 256ULL *
241 : (start[3] + 256ULL * (start[4] + 256ULL * (start[5] + 256ULL *
242 : (start[6] + 256ULL * start[7])))))));
243 : }
244 :
245 : static const uint8_t index_registers[] = {
246 : /* Note how REG_RIZ falls out of the pattern. */
247 : REG_RAX, REG_RCX, REG_RDX, REG_RBX,
248 : REG_RIZ, REG_RBP, REG_RSI, REG_RDI,
249 : REG_R8, REG_R9, REG_R10, REG_R11,
250 : REG_R12, REG_R13, REG_R14, REG_R15
251 : };
252 :
253 : #endif /* NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_RAGEL_DECODING_H_ */
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